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Research

EvolvI.T’s researchers have participated in many research projects for the last years. Our work is published in different international academic journals and conference proceedings.Some examples of our research work is illustrated below:

  1. Matrix Codes for Reliable and Cost Efficient Memory Chips Accepted for publication, IEEE TVLSI
  2. A novel error correction technique for adjacent errors 10th European Conference on Radiation Effects on Components and Systems – RADECS 2009
  3. Reliability Aware Yield Improvement Technique for Nanotechnology Based Circuits 22nd annual symposium on Integrated circuits and system design SBCCI ‘09, Natal, Brazil, September 2009 (Best Paper Award).
  4. A Fast Error Correction Technique for Matrix Multiplication Algorithms International Online Testing Symposium (IOLTS 09), Lisbon, Portugal, June 2009.
  5. Increasing Memory Yield in Future Technologies through Innovative Design IEEE International Symposium on Quality Electronic Design. (ISQED 09) March 2009
  6. Multiple Event Upsets Aware FPGAs Using Protected Schemes Dagstuhl Seminar Proceedings on Fault-Tolerant Distributed Algorithms on VLSI Chips, Dagstuhl, Germany, 13 March 2009.
  7. Single Element Correction in Sorting Algorithms with Minimum Delay Overhead‘ At the 10th IEEE Latin-American Test Workshop (LATW09), 2-5, March 2009.
  8. Minimizing the Recomputation Time in Soft Error Tolerant Matrix Multiplication Algorithms At the 1st HiPEAC Workshop on Design for Reliability (DFR’09) , January 2009
  9. ultiple SEU Tolerance in LUTs of FPGAs Using Protected Schemes8th European Workshop on Radiation Effects on Components and Systems (RADECS08), Sept. 2008
  10. Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. IEEE International On-Line Testing Symposium. July 2008.
  11. Area Reliability trade-off in Improved Reed Muller Coding SAMOS VIII Workshop, Samos, Greece, July 23-26, 2008
  12. Yield Improvement and Power Aware Low Cost Memory Chips Workshop on Radiation Effects and Fault Tolerance in Nanometer Technologies at Computing Frontiers 2008, Ischia, Italy, May 3-5 , 2008
  13. Algorithm Level Fault Tolerance: a Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. IEEE VLSI Test Symposium (VTS) 2008, San Diego California, USA, 27th April 2008
  14. Merging Built-in Current Sensor with H-Tree Architecture for SRAM Reliability Improvement, Proceedings of IEEE Latin American Test Workshop (LATW), Puebla Mexico, 17-20 February 2008.
  15. Single Error Correcting Finite Field Multipliers over GF(2m), Proceedings of 21st Conference on VLSI Design
  16. Working at Algorithm Level to Minimize Recomputation Time when Coping with Long Duration Transients DECIDE 2007, Rio, Brasil December 15-17, 2007
  17. High Defect Tolerant Low Cost Memory Chips, Proceedings of IEEE International System on Chip Conference (SOCC 07), Hsinchu, Taiwan, 26-29 Sept. 2007
  18. Improved Decoding Algorithm for High Reliable Reed Muller Coding Proceedings of IEEE International System on Chip Conference (SOCC 07), Hsinchu, Taiwan, 26-29 Sept. 2007
  19. Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2007, Rome, Italy, 26-28 Sept 2007
  20. Novel Soft Error Robust Power Aware Memory Designs International IEEE East West Design & Test Symposium (EWDTS’ 07), Yerevan, Armenia, 7-10 September 2007.
  21. Yield Improvement for High Defect Rate Nanotechnology Circuits International IEEE East West Design & Test Symposium (EWDTS’ 07), Yerevan, Armenia, 7-10 September 2007.
  22. A Soft Error Robust and Power Aware Memory Design, in Proceedings of the 20th Symposium on Integrated Circuits and Systems Design – SBCCI 2007, September 2007.
  23. Highly Reliable Power Aware Memory Design Proceedings of IEEE International On-Line Testing Symposium 2007 (IOLTS), Hersonisos of Heraklion, Crete, Greece, July 20-24, 2007.
  24. Online Detection and Correction of Soft-Errors in LUTs of SRAM-based FPGAs Proceedings of European Test Symposium (ETS), Freiburg, Germany, May 20-24, 2007.
  25. Efficient Method to Tolerate Multiple Bit Upsets in SRAM Memory Proceedings of European Test Symposium (ETS), Freiburg, Germany, May 20-24, 2007
  26. Multiple Upsets Tolerance in SRAM Memory, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, USA, 27-30 May, 2007.
  27. CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs , Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) ,New Orleans, USA, 27-30 May, 2007.
  28. Non-square Meshes for Improved Yield in Nanotechnology Circuits Proceedings of IEEE Latin American Test Workshop (LATW), Cuzco, Peru, 11 – 14, March 2007
  29. Fast Reed Muller Decoding for Multi-Bit Upset Aware Memory Designs Proceedings of IEEE Latin American Test Workshop (LATW), Cuzco, Peru, 11 – 14, March 2007
  30. Fast SEU Detection and LUT Configuration Bits of SRAM-based FPGAs, Proceedings of 14th IEEE Reconfigurable Architecture Workshop, in association with IPDPS, California, USA, 26-27 March, 2007.